(1) Field of the Invention
The present invention relates to a method and apparatus for determining placement coordinates of a circuit element (cell) at a time of design of an integrated circuit such as LSI, or a circuit on a printed wiring board.
(2) Description of the Related Art
In general, in order to design an integrated circuit such as LSI, a logic design is carried out depending upon a specification meeting functions of the LSI to be designed, and a packaging design is carried out depending upon a netlist obtained according to the logic design. In the packaging design, circuit elements (often referred to as cells) are placed depending upon the netlist, thereafter performing wiring among the placed circuit elements.
Moreover, the netlist has as information an input signal, an output signal, and interconnection of the circuit elements required for the signals, and is used for automatic placement or automatic wiring in the integrated circuit.
Further, in a conventional circuit element placement system, the netlist given by the logic design is directly used, and all unplaced circuit elements are concurrently handled and placed with consideration given to the entire circuit. Therefore, all the circuit elements become candidates for placement and movement at the same level.
However, in the above conventional circuit element placement system, all the unplaced circuit elements are concurrently handled so that an increase in circuit scale results in a reduction in processing speed and an increase in amount of memory. In addition, the concurrent handling of the entire circuit requires vast amounts of calculation in order to meet a delay constraint.
When a floor plan is manually executed, it is very difficult to predict whether or not the wiring can completely be performed, or predict whether or not the delay constraint can be met. Further, even in case of automatic schematic placement of the cells, a long processing time may be required depending upon an amount of handled data. It is thereby impossible to obtain a short turnaround time at a floor plan level.
Further, when an LSI chip to be designed is divided into a plurality of areas (blocks), and the circuit elements are placed, it is necessary to predict what placement is made in the respective blocks in order to determine points where the net passes across boundaries of the blocks. If the floor plan is manually executed, cell placement in the block is not made at the time. Thus, it is impossible to automatically find the points where the net passes across the boundaries of the blocks. In another system of finding the points where the net passes across the boundaries of the blocks after the schematic placement of the cells, a long time is required for the placement itself of the cells in case of a large circuit scale.
Further, since the given netlist is used in the original form in the prior art, the increase in circuit scale significantly extends an object to be considered, resulting in an extremely long processing time. Additionally, when various constraints are given, it is very hard to meet all the constraints because of the concurrent consideration of the entire circuit.
Besides, in the conventional system, all the cells become candidates for placement and movement at the same level so that, in many cases, the cells are placed without consideration to a configuration of the entire circuit. As a result, after automatic placement of the cells, there are caused problems in that, for example, a wiring length is excessively extended, and the delay constraint cannot be met.